Topics
DSE
Design Space Exploration
ERC
Electrical Rule Checking
FPGA
Field-Programmable Gate Arrays
MC
Model Checking
International Reviews
FPGA
DSE
Bruno Ferres, Olivier Muller, Frédéric Rousseau, A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. Accepted at ACM Transactions on Design Automation of Electronic Systems (TODAES) on 23 March 2023. Author version on ArXiV.
International Conferences and Workshops
ERC
MC
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond, Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. Short paper (2 pages) and poster. In Design, Automation and Test in Europe Conference & Exhibition (DATE) - Late Breaking Results track. 2023.
FPGA
DSE
Bruno Ferres, Olivier Muller, Frédéric Rousseau, Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. In Proc. of the 32nd International Workshop on Rapid System Prototyping (RSP'2021), Virtual event, 2021.
FPGA
DSE
Bruno Ferres, Olivier Muller, Frédéric Rousseau, Chisel Usecase: Designing General Matrix Multiply for FPGA. In Proc. of the 16th International Symposium on Applied Reconfigurable Computing (ARC 2020), Toledo, Spain, 2020.
PhD Thesis
FPGA
DSE