If you are interested in my research activities, do not hesitate to contact me to discuss opportunities for an internship, a thesis or a postdoc (even if no job proposal does fit your need!).


I am currently involved in the following research projects:

"Formal Verification of Integrated Circuits at Transistor Level" - industrial collaboration with LIP (Lyon) and Aniah
"Hardware and Software Security of Embedded Systems" - ANR Arsene - PEPR CyberSécurité
"Collaborative Action on Timing Interference" - ARN CAOTIC



PhD Students

2022 - now
Oussama Oulkaid
"Formal Verification Techniques for Electrical Rule Checking of Integrated Circuits"
Industrial thesis supervised by Matthieu Moy, HDR (LIP), and advised with Pascal Raymond (Verimag) and Mehdi Khosravian (Aniah).
LIP, Verimag, Aniah
Grenoble & Lyon
Internships
2024
(2 months)
Adnane El-Asli (2A Grenoble INP - Ensimag)
"Mapping Stream Processing Application to MLIR Vectorial Dialects"
with Laure Gonnord
Verimag & LCIS (Valence)
2024
(2 months)
Zoë Courvoisier-Clément (3A Grenoble INP - Esisar)
"Theory and Practice of Vectorial Extension for Stream Processing"
with Laure Gonnord
Verimag & LCIS (Valence)
2024
(2 months)
Mathias Gilbert (2A ENSTA Paris)
"Implémentation, vérification et préservation de de contre-mesures contre l’injection de fautes"
with Marie-Laure Potet & Basile Pesin
Verimag
2022
(4 months)
Oussama Oulkaid (M2 MOSIG, UGA)
"Applying Formal Methods to Circuit Electric Verification"
with Matthieu Moy, Pascal Raymond, Mehdi Khosravian
LIP, Verimag, Aniah
2021
(3 months)
Maxime Martin (1A Grenoble INP - Ensimag)
"Using Hardware Construction Languages to Implement Parametric Neural Network Accelerators on FPGA"
with Frédéric Pétrot
TIMA
2021
(6 months)
Jichen Liang (5A Polytech Grenoble)
"Improving High Level Estimators for an FPGA Design Space Exploration Framework"
with Olivier Muller
TIMA
2021
(3 months)
Paul Lagarosse (2A Grenoble INP - Ensimag)
"Implementing Parametric Computation Kernels on FPGA with Chisel"
with Olivier Muller
TIMA


Topics

DSE
Design Space Exploration
ERC
Electrical Rule Checking
FPGA
Field-Programmable Gate Arrays
MC
Model Checking
International Reviews

2023
FPGA
DSE
Bruno Ferres, Olivier Muller, Frédéric Rousseau, A Chisel Framework for Flexible Design Space Exploration through a Functional Approach. In ACM Transactions on Design Automation of Electronic Systems (TODAES). Author version on ArXiV.
International Conferences and Workshops

2024
ERC
MC
Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio, Gabriel Radanne, A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. In Design, Automation and Test in Europe Conference & Exhibition (DATE). 2024.
2023
ERC
MC
Bruno Ferres, Oussama Oulkaid, Ludovic Henrio, Mehdi Khosravian, Matthieu Moy, Gabriel Radanne, Pascal Raymond, Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. Short paper (2 pages) and poster. In Design, Automation and Test in Europe Conference & Exhibition (DATE) - Late Breaking Results track. 2023.
2021
FPGA
DSE
Bruno Ferres, Olivier Muller, Frédéric Rousseau, Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration. In Proc. of the 32nd International Workshop on Rapid System Prototyping (RSP'2021), Virtual event, 2021.
2020
FPGA
DSE
Bruno Ferres, Olivier Muller, Frédéric Rousseau, Chisel Usecase: Designing General Matrix Multiply for FPGA. In Proc. of the 16th International Symposium on Applied Reconfigurable Computing (ARC 2020), Toledo, Spain, 2020.

PhD Thesis