November 2023
Our latest work "A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving" has been accepted to DATE'24!
October 2023
Check my "Research" page for two internship proposals about low-level security of embedded systems, and one proposal about formal verification of integrated circuits.
September 2023
I have been appointed as Associate Professor at Verimag/UGA
I graduated from Grenoble INP - Ensimag in 2018, where I studied Embedded Systems and Software, and Université Grenoble Alpes, where I studied CyberSecurity. My PhD researches were then directed by Frédéric Rousseau and supervised by Olivier Muller, between 2018 and 2022, in the SLS team at TIMA lab. We aimed at using the emerging paradigm of Hardware Construction Languages to build a flexible exploration methodology, and provided a PoC framework based on Chisel, as well as an applicative benchmark. From March 2022 to August 2023, I was a post doctoral fellow at LIP laboratory (Lyon), in the CASH team. I worked on formal verification of electronical circuits (ERC) at transistor level, in collaboration with Aniah, a Grenoble-based company, and Verimag laboratory.
Since September 2023, I am an Associate Professor (MCF) in Grenoble. I'm doing my research at Verimag, and I'm teaching at Université Grenoble Alpes (UGA), mainly in UFR IM²AG.
Since September 2023, I am an Associate Professor (MCF) in Grenoble. I'm doing my research at Verimag, and I'm teaching at Université Grenoble Alpes (UGA), mainly in UFR IM²AG.
Contact
Email address: bruno[dot]ferres[at]univ-grenoble-alpes[dot]fr
Phone number: +33 4 57 42 22 34
Mail address:
Verimag
Bâtiment IMAG
Université Grenoble Alpes
150 place du Torrent
38401 Saint Martin d’Hères
FRANCE
