I’ve been a PhD student at TIMA-SLS from October, 2018 to March, 2022, after graduating from Grenoble INP - Ensimag, where I studied Embedded Systems and Software, and Université Grenoble Alpes, where I studied CyberSecurity.
My PhD researches were directed by Frédéric Rousseau and supervised by Olivier Muller, and aimed at using the emerging paradigm of Hardware Construction Languages to build a flexible exploration methodology, along with a PoC framework based on Chisel.

Since March 2022, I'm a post doc at LIP laboratory (Lyon), in the CASH team. I'm working on formal verification of electronical circuits at transistor level.

Useful links: My resume / SLS team website / CASH team website

Professional Experience
2022 - now
Post doctoral searcher
Formal verification of electrical rules at transistor level
2018 - 2022
PhD Thesis
Hardware Construction Language based design methodology for FPGA circuits
TIMA (UGA & Grenoble INP), Grenoble
2018 (6 months)
End of Study Project (internship)
Web security
Edifixio, Grenoble
2017 (3 months)
Engineering internship
Data science
SAP SE, Waldorf (Germany)
2015 (3 months)
Internship & fixed-term job
Web development and database management
Matooma, Montpellier
2018 - 2022
PhD thesis prepared at TIMA laboratory, in the System Level Synthesis (SLS) team.
Topic: "Leveraging Hardware Construction Languages for Flexible Design Space Exploration on FPGA"
Université Grenoble Alpes
2017 - 2018
Master in CyberSecurity
Université Grenoble Alpes
2015 - 2018
Engineering Degree in Computer Science and Applied Mathematics
Major in Embedded Software and Systems
Grenoble INP - Ensimag
QECE (Quick Exploration using Chisel Estimators)
Framework which allows the users to define adaptable estimation methodologies for digital circuits, and flexible design space exploration strategies.
Benchmark of FPGA representative applications, used to demonstrate the usability of QECE on various use cases.
PhD manuscript - Université Grenoble Alpes
LaTeX sources for the generation of my PhD dissertation.